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28C17A
16K (2K x 8) CMOS EEPROM
FEATURES
* Fast Read Access Time--150 ns * CMOS Technology for Low Power Dissipation - 30 mA Active - 100 A Standby * Fast Byte Write Time--200 s or 1 ms * Data Retention >200 years * High Endurance - Minimum 104 Erase/Write Cycles * Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches * Data Polling; Ready/Busy * Chip Clear Operation * Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit * Electronic Signature for Device Identification * 5-Volt-Only Operation * Organized 2Kx8 JEDEC Standard Pinout - 28 Pin Dual-In-Line Package - 32-Pin PLCC Package - 28-Pin Thin Small Outline Package (TSOP) 8x20mm - 28-Pin Very Small Outline Package (VSOP) 8x13.4mm * Available for Extended Temperature Ranges: - Commercial: 0C to +70C - Industrial: -40C to +85C
PACKAGE TYPES
RDY/BSY NC A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
*1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vcc WE NC A8 A6 5 A9 A5 6 NC A4 7 A3 8 OE A10 A2 9 A1 10 CE A0 11 I/O7 NC 12 I/O6 I/O0 13 I/O5 I/O4 I/O3
2 RDY/BSY 1 NU
32 Vcc 31 WE 18 19
4 A7 3 NC
30 NC 29 A8 28 A9 27 NC 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6 20
14
15
16
* Pin 1 indicator on PLCC on top of package
OE NC A9 A8 NC WE Vcc RDY/BSY NC A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14
22 23 24 25 26 27 28 1 2 3 4 5 6 7
I/O1 I/O2 Vss NU I/O3 I/O4 I/O5
17
DIP/SOIC
PLCC
28 27 26 25 24 23 22 21 20 19 18 17 16 15
21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2
A10 CE I/07 I/06 I/05 I/04 I/03 Vss I/02 I/01 I/00 A0 A1 A2
TSOP
OE NC A9 A8 NC WE VCC RDY/BSY NC A7 A6 A5 A4 A3
VSOP
DESCRIPTION
The Microchip Technology Inc. 28C17A is a CMOS 16K nonvolatile electrically Erasable PROM. The 28C17A is accessed like a static RAM for the read or write cycles without the need of external components. During a "byte write", the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wiredor systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications.
BLOCK DIAGRAM
I/O0 I/O7
VSS VCC
CE
OE WE
Rdy/ Busy
Data Protection Circuitry Chip Enable/ Output Enable Control Logic
Auto Erase/Write Timing
Data Poll
Input/Output Buffers
Program Voltage Generation
A0
L a t c h e s
A10
Y Decoder
Y Gating
X Decoder
16K bit Cell Matrix
(c) 1996 Microchip Technology Inc.
DS11127G-page 1
This document was created with FrameMaker 4 0 4
28C17A
1.0
1.1
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS*
TABLE 1-1:
Name A0 - A10 CE OE WE I/O0 - I/O7 RDY/Busy VCC VSS NC NU
PIN FUNCTION TABLE
Function Address Inputs Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy +5V Power Supply Ground No Connect; No Internal Connection Not Used; No External Connection is Allowed
VCC and input voltages w.r.t. VSS ....... -0.6V to + 6.25V Voltage on OE w.r.t. VSS ..................... -0.6V to +13.5V Voltage on A9 w.r.t. VSS ...................... -0.6V to +13.5V Output Voltage w.r.t. VSS ................ -0.6V to VCC+0.6V Storage temperature .......................... -65C to +125C Ambient temp. with power applied ....... -50C to +95C
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
READ/WRITE OPERATION DC CHARACTERISTICS
VCC = +5V 10% Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C
Parameter Input Voltages Input Leakage Input Capacitance Output Voltages Output Leakage Output Capacitance Power Supply Current, Active Power Supply Current, Standby
Status Logic `1' Logic `0' -- -- Logic `1' Logic `0' -- -- TTL input
Symbol VIH VIL ILI CIN VOH VOL ILO COUT ICC
Min 2.0 -0.1 -10 -- 2.4
Max Vcc+1 0.8 10 10
Units V V A pF V V A pF mA mA mA A
Conditions
VIN = -0.1V to Vcc +1 VIN = 0V; Tamb = 25C; f = 1 MHz IOH = -400 A IOL = 2.1 mA VOUT = -0.1V to VCC +0.1V VIN = 0V; Tamb = 25C; f = 1 MHz f = 5 MHz (Note 1) VCC = 5.5V; CE = VIH (0C to +70C) CE = VIH (-40C to +85C) CE = VCC-0.3 to Vcc +1
0.45 -10 -- -- -- 10 12 30 2 3 100
ICC(S)TTL TTL input TTL input ICC(S)TTL CMOS input ICC(S)CMOS
Note 1: AC power supply current above 5MHz: 1mA/MHz.
DS11127G-page 2
(c) 1996 Microchip Technology Inc.
28C17A
TABLE 1-3: READ OPERATION AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature:
28C17A-15
VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C
28C17A-20 28C17A-25
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE High to Output Float Output Hold from Address, CE or OE, whichever occurs first. Endurance
Symbol Min tACC tCE tOE tOFF tOH -- -- -- 0 0 Max 150 150 70 50 -- Min -- -- -- 0 0 Max 200 200 80 55 -- Min -- -- -- 0 0 Max 250 250 100 70 --
Units ns ns ns ns ns
Conditions OE = CE = VIL OE = VIL CE = VIL
--
1M
--
1M
--
1M
--
cycles
25C, Vcc = 5.0V, Block Mode (Note)
Note: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1:
VIH Address VIL VIH CE VIL
READ WAVEFORMS
Address Valid
tCE(2)
VIH OE VIL VOH Data VOL tACC VIH WE VOL tOE(2) High Z tOFF(1,3) tOH Valid Output High Z
Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested
(c) 1996 Microchip Technology Inc.
DS11127G-page 3
28C17A
TABLE 1-4: BYTE WRITE AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise/Fall Times: Ambient Temperature: Parameter Address Set-Up Time Address Hold Time Data Set-Up Time Data Hold Time Write Pulse Width Write Pulse High Time OE Hold Time OE Set-Up Time Data Valid Time Time to Device Busy Write Cycle Time (28C17A) Write Cycle Time (28C17AF) Symbol tAS tAH tDS tDH tWPL tWPH tOEH tOES tDV tDB tWC tWC Min 10 50 50 10 100 50 10 10 -- 2 -- -- VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C Max -- -- -- -- -- -- -- -- 1000 50 1 200 Units ns ns ns ns ns ns ns ns ns ns ms s 0.5 ms typical 100 s typical Note 2 Note 1 Remarks
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the positive edge of CE or WE, whichever occurs first 2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH after the positive edge of WE or CE, whichever occurs first.
FIGURE 1-2:
PROGRAMMING WAVEFORMS
VIH
Address VIL VIH CE, WE VIL tDV Data In VIH VIL tOES VIH OE VIL tOEH VOH Rdy/Busy VOL tWC tDB Busy Ready tDS tAS tAH tWPL tDH
DS11127G-page 4
(c) 1996 Microchip Technology Inc.
28C17A
FIGURE 1-3:
VIH
Address VIL Address Valid t ACC t CE t WPH
DATA POLLING WAVEFORMS
Last Written Address Valid
VIH
CE VIL
VIH
WE VIL
t WPL t OE
VIH
OE VIL
t DV VIH
Data VIL Data In Valid t WC I/O7 Out True Data Out
FIGURE 1-4:
VIH CE VIL VH OE VIH VIH WE VIL
CHIP CLEAR WAVEFORMS
tS
tW
tH
tW = 10ms tS = tH = 1s VH = 12.0V 0.5V
TABLE 1-5:
Mode Chip Clear Extra Row Read Extra Row Write
SUPPLEMENTARY CONTROL
CE VIL VIL * OE VH VIL VIH WE VIL VIH * A9 X A9 = VH A9 = VH Vcc VCC VCC VCC Data Out Data In I/OI
Note 1: VH = 12.0V 0.5V
* Pulsed per programming waveforms.
(c) 1996 Microchip Technology Inc.
DS11127G-page 5
28C17A
2.0 DEVICE OPERATION
2.4 Write Mode
The Microchip Technology Inc. 28C17A has four basic modes of operation--read, standby, write inhibit, and byte write--as outlined in the following table. Operation Mode Read Standby Write Inhibit Write Inhibit Write Inhibit Byte Write Byte Clear CE L H H X X L OE L X X L X H WE H X X X H L I/O DOUT High Z High Z High Z High Z DIN Rdy/Busy (1) H H H H H L The 28C17A features Data polling to signal the completion of a byte write cycle. During a write cycle, an attempted read of the last byte written results in the data complement of I/O7 (I/O0 to I/O6 are indeterminable). After completion of the write cycle, true data is available. Data polling allows a simple read/compare operation to determine the status of the chip eliminating the need for external hardware. The 28C17A has a write cycle similar to that of a Static RAM. The write cycle is completely self-timed and initiated by a low going pulse on the WE pin. On the falling edge of WE, the address information is latched. On rising edge, the data and the control pins (CE and OE) are latched. The Ready/Busy pin goes to a logic low level indicating that the 28C17A is in a write cycle which signals the microprocessor host that the system bus is free for other activity. When Ready/Busy goes back to a high, the 28C17A has completed writing and is ready to accept another cycle.
2.5
Data Polling
Automatic Before Each "Write"
Note 1: Open drain output. 2: X = Any TTL level.
2.1
Read Mode
The 28C17A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and is used to gate data to the output pins independent of device selection. Assuming that addresses are stable, address access time (tACC) equal to the delay from CE to output (tCE). Data is available at the output tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC-tOE.
2.6
Electronic Signature for Device Identification
An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9 to 12V 0.5V and using address locations 7EO to 7FF, the additional bytes can be written to or read from in the same manner as the regular memory array.
2.7
Chip Clear
2.2
Standby Mode
All data may be cleared to 1's in a chip clear cycle by raising OE to 12 volts and bringing the WE and CE low. This procedure clears all data, except for the extra row.
The 28C17A is placed in the standby mode by applying a high signal to the CE input. When in the standby mode, the outputs are in a high impedance state, independent of the OE input.
2.3
Data Protection
In order to ensure data integrity, especially during critical power-up and power-down transitions, the following enhanced data protection circuits are incorporated: First, an internal VCC detect (3.3 volts typical) will inhibit the initiation of non-volatile programming operation when VCC is less than the VCC detect circuit trip. Second, there is a WE filtering circuit that prevents WE pulses of less than 10 ns duration from initiating a write cycle. Third, holding WE or CE high or OE low, inhibits a write cycle during power-on and power-off (VCC).
DS11127G-page 6
(c) 1996 Microchip Technology Inc.
28C17A
28C17A Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices.
28C17A F
T
-
15
I
/P Package: L P TS VS = = = = Plastic Leaded Chip Carrier (PLCC) Plastic DIP (600 mil) Thin Small Outline Package (TSOP) 8x20mm Very Small Outline Package (VSOP) 8x13.4mm
Temperature Range: Access Time:
Blank = 0C to +70C I = -40C to +85C 15 20 25 Blank T 150 ns 200 ns 250 ns Tube Tape and Reel "L" and "SO"
Shipping: Option: Device:
Blank = twc = 1ms F = twc = 200 s
28C17A
2K x 8 CMOS EEPROM
(c) 1996 Microchip Technology Inc.
DS11127G-page 7
WORLDWIDE SALES & SERVICE
AMERICAS
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ASIA/PACIFIC
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EUROPE
United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleone Pas Taurus 1 Viale Colleoni 1 20041 Agrate Brianza Milan Italy Tel: 39 39 6899939 Fax: 39 39 689 9883
JAPAN
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122
9/3/96
All rights reserved. (c) 1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS11127G-page 8
(c) 1996 Microchip Technology Inc.

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